High performance integrated circuit (IC) packages are well known in the art. Improvements in IC packages are driven by demands for increased thermal and electrical performance, decreased size and cost of manufacture.
Typically, array packaging such as ball grid array (BGA) packages provide for a high density package. FIG. 1 shows a typical prior art package in which a copper leadframe 20 is etched to approximately half the leadframe thickness to form a pocket for the semiconductor die 22. The etch-down process results in an etch-down pocket with a radius 24 at each pocket corner (where the base 26 on which the semiconductor die 22 is mounted, meets each side 28). Each IC package includes a pocket that is large enough to accommodate the die 22 and the radius 24. Thus, the radius 24 limits the reduction in the size of the pocket.
Prior art IC packages such as that shown in FIG. 1, are manufactured such that each of the contacts lie in a single plane. Thus, the solder ball contacts 30 on the leadframe lie in the same plane as the solder ball contacts 30 on the semiconductor die. The half etch depth of the leadframe 20 is important in order to ensure that all of the solder ball contacts 30 lie in a single plane. The half etch depth is difficult to accurately control and therefore manufacture of the IC package with solder ball contacts 30 in a single plane is difficult.
Accordingly, it is an object of an aspect of the present invention to provide a method for manufacturing an IC package that obviates or mitigates at least some of the disadvantages of the prior art.